Ways to assign signals in Verilog

1. Continuous assignment (assign)
　wire a;
　assign a = 1'b1; //behaves like a wire

2. Procedural assignemnt (always)
　a). blocking assignment
　　reg a, b;
　　a = 1'b1; //will block next assignment only in sequential blocks
　　b = 1'b0;
　b). non-blocking assignment
　　reg a, b;
　　a <= 1'b1; //all non-blocking assignemnts will be executed at 　　　b <= 1'b0; //the END of this update event.
　　Because non-blocking assignments are executed at the end of update event, if they are mixed with blocking assigments, non-blocking assignments will be executed after all blocking assignments.
　　If multiple non-blocking assignments are used to assign the same variable in a block, the order of assignments will be hornored.
　　reg a;
　　a <= 1'b1;
　　a <= 1'b0; //a is 0 finally 　　If multiple non-blocking/blocking assignments are used to assign the same variable in different blocks, and the order of their executions can not be decided, then the final value of this variable can not be determined.
　　reg a;
　　initial a <= 1'b1;
　　initial a <= 1'b0; //a is uncertain
　　However, if the order of their executions can be determined, the final value of the variable is determined.
　　reg a;
　　initial #8 a <= #8 1'b1; //@16, a is set to 1, scheduled @8
　　initial #10 a <= #6 1'b0; //@16, a is set to 0, scheduled @10 　
　　a would be 0 finally because the second assignemnt is scheduled later.
3. Procedural continuous assignment (assign/deassign, force/release)
　　assign procedural continuous assignment will override all previous procedural assignments to the same variable. deassign will cancel this assignment.
　　force/release have the similar function with the exception that they can be used on wires as well.
　　module dff (q,d,clear, preset, clock);
　　input d, clear, preset, clock;
　　output q;
　　reg q;

　　always @(clear or preset)
　　　　if(!clear) assign q = 0;
　　　　else if (!preset) assign q = 1;
　　　　else deassign q;

　　always @(posedge clock)
　　　　q = d;
　　endmodule