skip to main
|
skip to sidebar
Euisi's Blog
4/21/2007
Logic Calucation in Veirlog
~z = x;
~X = X;
0&Z = 0&X = 0;
1&Z = 1&X = X;
Z&1 = Z&Z = Z&X = X;
X&1 = X&Z = X&X = X;
Z|0 = Z|Z = Z|X = X;
X|0 = X|Z = X|X = X;
Z^* = X^* = X;
Z~^* = X~^* = X;
No comments:
Post a Comment
Newer Post
Older Post
Home
Subscribe to:
Post Comments (Atom)
Technical Notes
eruisi
View my complete profile
Blog Archive
▼
2007
(16)
▼
April
(4)
Some tips for vi
Embed Perl into C/C++
Logic Calucation in Veirlog
Ways to assign signals in Verilog
►
March
(4)
►
February
(8)
►
2005
(12)
►
November
(2)
►
October
(1)
►
August
(1)
►
June
(2)
►
May
(2)
►
April
(1)
►
March
(1)
►
January
(2)
►
2004
(1)
►
December
(1)
Labels
Affirma
(1)
Annotation
(1)
ASIC
(8)
assignement
(1)
Astro
(1)
blocking
(1)
c
(3)
C++
(1)
Cadence
(1)
Calibre
(1)
chm
(1)
Clock
(1)
Clock Tree
(1)
debussy
(1)
EDA
(1)
encode
(1)
FSM
(2)
gps
(1)
ip
(1)
Linux
(6)
Mentor
(1)
mysql
(1)
non-blocking
(1)
Perl
(1)
PHP
(2)
PLI
(1)
pointer
(1)
port
(1)
proxy
(1)
reset
(1)
rpm
(1)
Samba
(1)
SDC
(1)
SDF
(1)
serendity
(1)
smalltalk
(1)
squid
(1)
swig
(1)
tcl
(2)
tcp
(1)
TLU
(1)
Verilog
(4)
Vi
(1)
Virtual
(1)
VLSI
(1)
VPI
(1)
Web
(2)
winxp
(3)
中文搜索
(1)
优化
(2)
版本管理
(1)
端口
(1)
No comments:
Post a Comment